1. Field of the Invention
The present invention relates to the field of data synchronizer and time base generator circuits, particularly for dual PLL data synchronization system.
2. Background Art
Mass storage for computer systems is typically provided by a magnetic or optical media storage system, such as rigid or flexible disk storage systems. In a magnetic system, a rotating disk having a magnetic media layer on the surface is accessed by a "read/write" head which is used to store and retrieve information from the disk surface. To store information on a magnetic media disk, flux reversals are induced in the magnetic particles comprising the disk's surface. When a magnetic read/write head is passed over the flux reversals, a signal is induced in the head which can be decoded to convey information stored on the disk. Typically, the magnetic flux reversals are interpreted as "ones" or "zeros" according to the coding algorithm.
In a preformatted, write-once, or rewritable optical disk drive, data is stored as a series of pits arranged in concentric or spiral tracks on a disk surface. The read/write head is replaced by a lens assembly which is used to project a light beam, (such as a laser beam), onto the disk surface. The light beam is modulated by the pits in the disk and the modulated light beam is reflected from the disk to an optical pick up device which can produce an output signal dependent on the modulation of the light beam. In a magneto-optical disk drive, magnetic domains are oriented so that the polarization of a read light beam is modulated and this modulated beam is detected. In an optical disk drive, a movable lens assembly is mounted on a relatively large base carriage. The base carriage is moved back and forth in a radial direction relative to the optical disk. The lens assembly moves radially relative to the disk and relative to the base carriage.
When information recorded on a hard disk is recovered, it is often in the form of bit stream. To accurately decode a serial bit stream, bit frames or bit windows must be accurately defined. A one-to-one correspondence exists between each bit and each frame or window. For a variety of reasons, errors can be introduced in data bit streams that may affect the amplitude and phase of the recovered signal. Amplitude errors can be minimized by use of an automatic gain control (AGC) circuit. A phase error, also known as "jitter," is a rotation of a symbol that does not change the magnitude of the symbol. This tends to force a data bit near or past a bit window boundary.
To maximize the efficiency of data recovery, the average bit position can be estimated with a decode window having a nominal center coinciding with the average center bit position of the data bit stream. However, problems still exist when the jitter causes the bit position to extend over a window edge.
To determine a decode window with acceptable timing accuracy, clock recovery circuits can be provided utilizing phase locking via a phase locked loop (PLL) to generate both edges of a window. A PLL circuit is implemented for synchronization to produce a clock signal equal in frequency to the data rate of the signal read from the disk media. The PLL circuit acquires the nominal frequency of the read signal and tracks deviations in its nominal frequency, thereby producing an output clock frequency that varies according to deviations of the reference frequency (frequency of the read signal). Thus,
For 3.5" 640 MByte type magneto-optical disks, the standard format uses the (1,7) RLL (Run Length Limited) coding in conjunction with PWM (Pit width Modulation) recording scheme in accordance with ISO (International Organization for Standardization) standards. FIG. 1 shows the PWM recording data and read signals. The read data is changed from `0` to `1` (or `1` to `0`) when the encoded data is `1`. Therefore, both rising and falling edges indicate the data signal on the media.
FIG. 2 shows a typical prior art read channel system, which consists of an analog front end, which comprises AGC 201, programmable equalizer filter 202, and data qualifier 204, a time base generator 210 and data synchronizer 206 and 207. Full wave rectifier 203 couples the output of equalizer filter 202 to AGC 201 in a feedback loop. An output of data qualifier 204 is coupled to PLL1 205 and data synchronizer 206. Another output of data qualifier 204 is coupled to PLL2 208 and data synchronizer 207. The data qualifier 204 transforms each valid analog read data pulses into a digital pulse, while preserving the relative time position of each valid pulse edge.
A reference signal F.sub.REF is coupled to time base generator 210, which is coupled to PLL3 209. The output of time base generator 210 is coupled to PLL1 205, PLL2 208, and CLOCK terminal. Both time base generator 210 and data synchronizers 206 and 207 are based on a PLL circuit. Time base generator 210 is programmed to provide a stable reference frequency for data synchronizers. The output clock of time base generator 210 can be either PLL3 209 output or time base generator's F.sub.REF input signal.
In PWM recordings for optical and magneto-optical disk, the read signal is sliced by the floating slice level in the data qualifier. The signal comprises both edges of the pit mark. The formed pit length depends on the recording conditions (write power, media, slew rate of the laser driver, etc.) and data pattern. Hence, both edges (leading edge and trailing edge) need to be treated independently. As both edges require separate PLLs, and are synchronized independently, the decode window margins may also vary.
There are usually 3 PLL circuits in a read channel circuit: 2 PLL circuits for the data synchronizer, and one PLL for the time base generator. The output clock of the time base generator 210 is used as the reference clock for the data synchronizer PLLs in the idle mode and write clock in write mode.
In this prior art method, the 3 PLL circuits in the chip are asynchronous. Also, it is inefficient to include 3 PLL circuits in a same chip since it requires bigger die size and may deteriorate the jitter performance of the clock outputs. Since the PLL circuit is an analog based solution (including VCO and phase detector), the circuit area is large compared to other circuits in the read channel IC.
Further, these prior art PLLs are locked asynchronously in read mode, requiring an isolation of the power lines and signal lines to avoid the cross-talk between signals. Thus, this prior art method requires a large chip size and dissipates much power.
Thus, there is a need in the art to overcome the shortcomings of the prior art data synchronizers and provide a data synchronizer that is compact in size and efficient in power consumption and can deliver an improved and reliable data synchronization capability.